Semiconductor memory devices for storing data can typically be categorized as either volatile memory devices or nonvolatile memory devices. Volatile memory devices lose their stored data when their power supplies are interrupted, however nonvolatile memory devices retain their stored data even when their power supplies are interrupted. Thus, nonvolatile memory devices are widely used in applications where the possibility of power supply interruption is present.
Conventional nonvolatile memory devices include a type of electrically erasable programmable read only memory (EEPROM) device typically referred to as a flash EEPROM device. Flash EEPROM devices typically include a semiconductor substrate of first conductivity type (e.g., P-type), spaced source and drain regions of second conductivity type (e.g., N-type) in the substrate, a channel region at a face of the substrate, between the spaced source and drain regions, a floating gate for storing charge carriers when the device is programmed and a control gate which overlies the floating gate, opposite the channel region. Conventional flash EEPROM integrated circuit memory devices may contain column-by-column arrays of NAND EEPROM cells having the general construction illustrated in cross-section and schematically by FIGS. 11.58 and 11.59 from a handbook by B. Prince et al. entitled Semiconductor Memories, John Wiley & Sons Ltd., pp. 603-604 (1991); and in an article by M. Momodomi et al. entitled An Experimental 4-Mbit CMOS EEPROM with a NAND Structured Cell, IEEE Journal of Solid State Circuits, Vol. 24, No. 5, p. 1238 October (1989). Typical schematic and cross-sectional layouts of arrays containing NAND EEPROM cells are also more fully described in commonly assigned U.S. Pat. No. 5,546,341 to Suh et al. entitled Nonvolatile Semiconductor Memory.
Operation of a flash EEPROM device is typically divided into three modes including programming, erasing and reading. Programming of a flash EEPROM device is typically achieved by biasing the drain region to a first positive bias, relative to the source region, and biasing the control gate to a second positive bias which is greater than the first positive bias. In the absence of any stored charge on the floating gate, these biases cause the formation of an inversion-layer channel of electrons at the face of the substrate, between the source and drain regions. As will be understood by those skilled in the art, the drain-to-source voltage accelerates these electrons through the channel to the drain region where they acquire sufficiently large kinetic energy and are typically referred to as "hot" electrons. The larger positive bias on the control gate also establishes an electrical field in a tunneling oxide layer which separates the floating gate from the channel region. This electric field attracts the hot electrons and accelerates them toward the floating gate, which is disposed between the control gate and the channel region, by a process known as tunneling. The floating gate then accumulates and traps the accumulated charge. Fortunately, the process of charging the floating gate is self-limiting. The negative charge that accumulates on the floating gate reduces the strength of the electric field in the tunneling oxide layer to the point where it is no longer capable of accelerating "hot" electrons from the drain side of the channel region.
As will be understood by those skilled in the art, the accumulation of a large quantity of trapped charge (electrons) on the floating gate will cause the effective threshold voltage (V.sub.th) of the field effect transistor comprising the source region, drain region, channel region and control gate to increase. If this increase is sufficiently large, the field effect transistor will remain in a nonconductive "off" state when a predetermined "read" voltage is applied to the control gate during a read operation (i.e., V.sub.th &gt;V.sub.read). In this state, known as the programmed state, the EEPROM device may be said to be storing a logic 0. Once programmed, the EEPROM device retains its higher threshold voltage even when its power supply is interrupted or turned off for long periods of time.
Erasing of the EEPROM device may also be achieved by removing the stored charge from the floating gate. The erasure process can be achieved, for example, by grounding the control gate and applying a positive bias to the substrate (e.g., 10-20 Volts). Accordingly, flash EEPROM devices typically require bulk erasure of large portions of an array of cells since the effects of applying a large substrate bias typically cannot be confined to a single EEPROM cell.
Reading of the EEPROM device is achieved by applying a predetermined read voltage (V.sub.read) to the control gate, typically via a word line connecting a row (i.e., page) of identical EEPROM devices or "cells", and applying a positive bias to the drain region, typically via a bit line connecting a column of identical EEPROM cells. If the EEPROM device is programmed, it will not conduct drain current (I.sub.ds) and the bit line will remain at the positive bias. However, if the EEPROM device has not been programmed (or has been erased), it will heavily conduct and pull the bit lie down to ground potential (GND). In this state, the EEPROM device may be said to be storing a logic 1. Thus, by monitoring the bit line current and voltage, the programmed state (i.e., 1 or 0) of the EEPROM device can be determined.
During the performance of a reading operation, it may become necessary to perform a page copy operation by copying data read from a first page of memory cells at a first address to a second page of memory cells at a second different address. As illustrated by FIG. 1, a conventional page copy operation typically includes the steps of reading data from a first page of memory cells 101 in an array 100 to a page buffer 300 and then to a storage device 400 external to the page buffer 300. Next, the data in the storage device 400 is returned to the page buffer 300 and then reprogrammed into the second page of memory cells 102 using conventional programming operations. The operations illustrated by FIG. 1 are more fully described by FIG. 2 which illustrates the timing of signals required to perform a conventional page copy operation. As will be understood by those skilled in the art, the signal CLE represents the command latch enable signal, the signal ALE represents the address latch enable signal, the signal WE represents the write enable signal and the signal RE represents the read enable signal. Referring now to FIG. 2, after applying a read command "00h" through an input/output (I/O) terminal during interval T1, addresses of three cycles are provided during interval T2 so that the memory device 100 outputs as a batch the data stored in all the memory cells of the first page 101 (designated by the addresses) through the bit lines. The output data is then sensed and temporarily retained by the page buffer 300 during interval T3. The read enable signal RE is then toggled to commence serial transfer of the retained data from the buffer 300 to the external storage device 400 during interval T4. A data loading command "80h" is then input and addresses of three cycles are applied during interval T5. The data stored in the storage device 400 in then loaded into the page buffer 300 during interval T6. Finally, a page programming command "10h" is inputted during interval T7 so that all memory cells in the second page 102 can be programmed during interval T8. Unfortunately, the page copy operations illustrated by FIG. 1 require external storage 400 and typically require that such external storage be loaded serially from the page buffer 300 and downloaded serially to the page buffer 300, which can very time consuming.
To address the limitations associated with the memory device and page copy operations illustrated by FIG. 1, alternative page copy operations were developed. For example, FIG. 3 illustrates a second conventional method for performing page copy operations. According to this method, a first page 101 of data is read into a page buffer 300 where it is retained in an inverted format. The retained data is then stored back into the memory 100 at an address of a second page 102. However, these page copy operations are limited because the copy of the original data from the first page is not stored as a "true" copy but is stored as an inverted copy. Accordingly, during subsequent read operations, it is possible for data errors to occur if the inverted copy is treated as a true copy.
Thus, notwithstanding the above described memory devices and methods for performing page copy operations, there continues to be a need for improved memory devices and methods for performing page copy operations which do not require external memory, serial loading or downloading operations and are not subject to the risk of data errors when true copies of data are not stored during page copy operations.